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UART I2C SPI 2 Registers Settings
Settings for registers of UART I2C SPI 2 Click driver. More...
Detailed Description
Settings for registers of UART I2C SPI 2 Click driver.
Macro Definition Documentation
◆ UARTI2CSPI2_BAUDRATE_115200
| #define UARTI2CSPI2_BAUDRATE_115200 115200ul |
◆ UARTI2CSPI2_BAUDRATE_1200
| #define UARTI2CSPI2_BAUDRATE_1200 1200ul |
UART I2C SPI 2 uart baud rate setting.
Specified setting for uart baud rate of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_BAUDRATE_14400
| #define UARTI2CSPI2_BAUDRATE_14400 14400ul |
◆ UARTI2CSPI2_BAUDRATE_19200
| #define UARTI2CSPI2_BAUDRATE_19200 19200ul |
◆ UARTI2CSPI2_BAUDRATE_230400
| #define UARTI2CSPI2_BAUDRATE_230400 230400ul |
◆ UARTI2CSPI2_BAUDRATE_2400
| #define UARTI2CSPI2_BAUDRATE_2400 2400ul |
◆ UARTI2CSPI2_BAUDRATE_38400
| #define UARTI2CSPI2_BAUDRATE_38400 38400ul |
◆ UARTI2CSPI2_BAUDRATE_460800
| #define UARTI2CSPI2_BAUDRATE_460800 460800ul |
◆ UARTI2CSPI2_BAUDRATE_4800
| #define UARTI2CSPI2_BAUDRATE_4800 4800ul |
◆ UARTI2CSPI2_BAUDRATE_57600
| #define UARTI2CSPI2_BAUDRATE_57600 57600ul |
◆ UARTI2CSPI2_BAUDRATE_9600
| #define UARTI2CSPI2_BAUDRATE_9600 9600ul |
◆ UARTI2CSPI2_BRGCFG_2XMODE
| #define UARTI2CSPI2_BRGCFG_2XMODE 0x10 |
◆ UARTI2CSPI2_BRGCFG_4XMODE
| #define UARTI2CSPI2_BRGCFG_4XMODE 0x20 |
UART I2C SPI 2 BRGCFG register setting.
Specified setting for BRGCFG register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_BRGCFG_FRACT_MASK
| #define UARTI2CSPI2_BRGCFG_FRACT_MASK 0x0F |
◆ UARTI2CSPI2_CLKSRC_CLK_TO_RTS
| #define UARTI2CSPI2_CLKSRC_CLK_TO_RTS 0x80 |
UART I2C SPI 2 CLKSRC register setting.
Specified setting for CLKSRC register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_CLKSRC_CRYSTAL_EN
| #define UARTI2CSPI2_CLKSRC_CRYSTAL_EN 0x02 |
◆ UARTI2CSPI2_CLKSRC_PLL_BYPASS
| #define UARTI2CSPI2_CLKSRC_PLL_BYPASS 0x08 |
◆ UARTI2CSPI2_CLKSRC_PLL_EN
| #define UARTI2CSPI2_CLKSRC_PLL_EN 0x04 |
◆ UARTI2CSPI2_CRYSTAL_FREQ
| #define UARTI2CSPI2_CRYSTAL_FREQ 1843200ul |
◆ UARTI2CSPI2_DEVICE_ADDRESS_A1A0_00
| #define UARTI2CSPI2_DEVICE_ADDRESS_A1A0_00 0x6C |
UART I2C SPI 2 device address setting.
Specified setting for device slave address selection of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_DEVICE_ADDRESS_A1A0_01
| #define UARTI2CSPI2_DEVICE_ADDRESS_A1A0_01 0x61 |
◆ UARTI2CSPI2_DEVICE_ADDRESS_A1A0_10
| #define UARTI2CSPI2_DEVICE_ADDRESS_A1A0_10 0x64 |
◆ UARTI2CSPI2_DEVICE_ADDRESS_A1A0_11
| #define UARTI2CSPI2_DEVICE_ADDRESS_A1A0_11 0x65 |
◆ UARTI2CSPI2_FIFO_LEN
| #define UARTI2CSPI2_FIFO_LEN 128 |
◆ UARTI2CSPI2_FLOWCTRL_SW_FLOW_MASK
| #define UARTI2CSPI2_FLOWCTRL_SW_FLOW_MASK 0xF0 |
◆ UARTI2CSPI2_FLOWCTRL_SW_FLOW_NO_FLOW
| #define UARTI2CSPI2_FLOWCTRL_SW_FLOW_NO_FLOW 0x00 |
UART I2C SPI 2 FLOWCTRL register setting.
Specified setting for FLOWCTRL register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_GLOBAL_CMD_DIS_EXT_REGMAP
| #define UARTI2CSPI2_GLOBAL_CMD_DIS_EXT_REGMAP 0xCD |
◆ UARTI2CSPI2_GLOBAL_CMD_EN_EXT_REGMAP
| #define UARTI2CSPI2_GLOBAL_CMD_EN_EXT_REGMAP 0xCE |
◆ UARTI2CSPI2_GLOBAL_CMD_TX0
| #define UARTI2CSPI2_GLOBAL_CMD_TX0 0xE0 |
UART I2C SPI 2 GLOBAL_CMD register setting.
Specified setting for GLOBAL_CMD register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_GLOBAL_CMD_TX1
| #define UARTI2CSPI2_GLOBAL_CMD_TX1 0xE1 |
◆ UARTI2CSPI2_GLOBAL_CMD_TX10
| #define UARTI2CSPI2_GLOBAL_CMD_TX10 0xEA |
◆ UARTI2CSPI2_GLOBAL_CMD_TX11
| #define UARTI2CSPI2_GLOBAL_CMD_TX11 0xEB |
◆ UARTI2CSPI2_GLOBAL_CMD_TX12
| #define UARTI2CSPI2_GLOBAL_CMD_TX12 0xEC |
◆ UARTI2CSPI2_GLOBAL_CMD_TX13
| #define UARTI2CSPI2_GLOBAL_CMD_TX13 0xED |
◆ UARTI2CSPI2_GLOBAL_CMD_TX14
| #define UARTI2CSPI2_GLOBAL_CMD_TX14 0xEE |
◆ UARTI2CSPI2_GLOBAL_CMD_TX15
| #define UARTI2CSPI2_GLOBAL_CMD_TX15 0xEF |
◆ UARTI2CSPI2_GLOBAL_CMD_TX2
| #define UARTI2CSPI2_GLOBAL_CMD_TX2 0xE2 |
◆ UARTI2CSPI2_GLOBAL_CMD_TX3
| #define UARTI2CSPI2_GLOBAL_CMD_TX3 0xE3 |
◆ UARTI2CSPI2_GLOBAL_CMD_TX4
| #define UARTI2CSPI2_GLOBAL_CMD_TX4 0xE4 |
◆ UARTI2CSPI2_GLOBAL_CMD_TX5
| #define UARTI2CSPI2_GLOBAL_CMD_TX5 0xE5 |
◆ UARTI2CSPI2_GLOBAL_CMD_TX6
| #define UARTI2CSPI2_GLOBAL_CMD_TX6 0xE6 |
◆ UARTI2CSPI2_GLOBAL_CMD_TX7
| #define UARTI2CSPI2_GLOBAL_CMD_TX7 0xE7 |
◆ UARTI2CSPI2_GLOBAL_CMD_TX8
| #define UARTI2CSPI2_GLOBAL_CMD_TX8 0xE8 |
◆ UARTI2CSPI2_GLOBAL_CMD_TX9
| #define UARTI2CSPI2_GLOBAL_CMD_TX9 0xE9 |
◆ UARTI2CSPI2_GLOBAL_IRQ_IRQ0
| #define UARTI2CSPI2_GLOBAL_IRQ_IRQ0 0x01 |
◆ UARTI2CSPI2_GLOBAL_IRQ_IRQ1
| #define UARTI2CSPI2_GLOBAL_IRQ_IRQ1 0x02 |
UART I2C SPI 2 GLOBAL_IRQ register setting.
Specified setting for GLOBAL_IRQ register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_I2C_UART_SEL_0
| #define UARTI2CSPI2_I2C_UART_SEL_0 0x20 |
◆ UARTI2CSPI2_I2C_UART_SEL_1
| #define UARTI2CSPI2_I2C_UART_SEL_1 0x10 |
◆ UARTI2CSPI2_I2C_UART_SEL_MASK
| #define UARTI2CSPI2_I2C_UART_SEL_MASK 0x30 |
◆ UARTI2CSPI2_IRDA_IRDA_EN
| #define UARTI2CSPI2_IRDA_IRDA_EN 0x01 |
◆ UARTI2CSPI2_IRDA_MIR
| #define UARTI2CSPI2_IRDA_MIR 0x08 |
◆ UARTI2CSPI2_IRDA_RX_INV
| #define UARTI2CSPI2_IRDA_RX_INV 0x10 |
◆ UARTI2CSPI2_IRDA_SIR
| #define UARTI2CSPI2_IRDA_SIR 0x02 |
◆ UARTI2CSPI2_IRDA_TX_INV
| #define UARTI2CSPI2_IRDA_TX_INV 0x20 |
UART I2C SPI 2 IRDA register setting.
Specified setting for IRDA register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_IRQ_CTS
| #define UARTI2CSPI2_IRQ_CTS 0x80 |
UART I2C SPI 2 IRQEN/IRQSTS register setting.
Specified setting for IRQEN/IRQSTS register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_IRQ_LSR_ERR
| #define UARTI2CSPI2_IRQ_LSR_ERR 0x01 |
◆ UARTI2CSPI2_IRQ_RX_EMPTY
| #define UARTI2CSPI2_IRQ_RX_EMPTY 0x40 |
◆ UARTI2CSPI2_IRQ_RX_TRG
| #define UARTI2CSPI2_IRQ_RX_TRG 0x08 |
◆ UARTI2CSPI2_IRQ_SP_CHR
| #define UARTI2CSPI2_IRQ_SP_CHR 0x02 |
◆ UARTI2CSPI2_IRQ_STS
| #define UARTI2CSPI2_IRQ_STS 0x04 |
◆ UARTI2CSPI2_IRQ_TX_FIFO_EMPTY
| #define UARTI2CSPI2_IRQ_TX_FIFO_EMPTY 0x20 |
◆ UARTI2CSPI2_IRQ_TX_TRG
| #define UARTI2CSPI2_IRQ_TX_TRG 0x10 |
◆ UARTI2CSPI2_LCR_EVEN_PARITY
| #define UARTI2CSPI2_LCR_EVEN_PARITY 0x10 |
◆ UARTI2CSPI2_LCR_FORCE_PARITY
| #define UARTI2CSPI2_LCR_FORCE_PARITY 0x20 |
◆ UARTI2CSPI2_LCR_PARITY_EN
| #define UARTI2CSPI2_LCR_PARITY_EN 0x08 |
◆ UARTI2CSPI2_LCR_RTS_BIT
| #define UARTI2CSPI2_LCR_RTS_BIT 0x80 |
UART I2C SPI 2 LCR register setting.
Specified setting for LCR register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_LCR_STOP_BITS_1
| #define UARTI2CSPI2_LCR_STOP_BITS_1 0x00 |
◆ UARTI2CSPI2_LCR_STOP_BITS_2_OR_1_5
| #define UARTI2CSPI2_LCR_STOP_BITS_2_OR_1_5 0x04 |
◆ UARTI2CSPI2_LCR_STOP_BITS_MASK
| #define UARTI2CSPI2_LCR_STOP_BITS_MASK 0x04 |
◆ UARTI2CSPI2_LCR_TX_BREAK
| #define UARTI2CSPI2_LCR_TX_BREAK 0x40 |
◆ UARTI2CSPI2_LCR_WORD_LENGTH_5
| #define UARTI2CSPI2_LCR_WORD_LENGTH_5 0x00 |
◆ UARTI2CSPI2_LCR_WORD_LENGTH_6
| #define UARTI2CSPI2_LCR_WORD_LENGTH_6 0x01 |
◆ UARTI2CSPI2_LCR_WORD_LENGTH_7
| #define UARTI2CSPI2_LCR_WORD_LENGTH_7 0x02 |
◆ UARTI2CSPI2_LCR_WORD_LENGTH_8
| #define UARTI2CSPI2_LCR_WORD_LENGTH_8 0x03 |
◆ UARTI2CSPI2_LCR_WORD_LENGTH_MASK
| #define UARTI2CSPI2_LCR_WORD_LENGTH_MASK 0x03 |
◆ UARTI2CSPI2_LSR_IRQ_CTS
| #define UARTI2CSPI2_LSR_IRQ_CTS 0x80 |
UART I2C SPI 2 LSR_IRQEN/LSR_IRQSTS register setting.
Specified setting for LSR_IRQEN/LSR_IRQSTS register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_LSR_IRQ_FRAME_ERR
| #define UARTI2CSPI2_LSR_IRQ_FRAME_ERR 0x08 |
◆ UARTI2CSPI2_LSR_IRQ_NOISE_INT
| #define UARTI2CSPI2_LSR_IRQ_NOISE_INT 0x20 |
◆ UARTI2CSPI2_LSR_IRQ_PARITY
| #define UARTI2CSPI2_LSR_IRQ_PARITY 0x04 |
◆ UARTI2CSPI2_LSR_IRQ_R_BREAK
| #define UARTI2CSPI2_LSR_IRQ_R_BREAK 0x10 |
◆ UARTI2CSPI2_LSR_IRQ_R_OVERR
| #define UARTI2CSPI2_LSR_IRQ_R_OVERR 0x02 |
◆ UARTI2CSPI2_LSR_IRQ_R_TIMEOUT
| #define UARTI2CSPI2_LSR_IRQ_R_TIMEOUT 0x01 |
◆ UARTI2CSPI2_MODE1_AUTO_SLEEP
| #define UARTI2CSPI2_MODE1_AUTO_SLEEP 0x40 |
UART I2C SPI 2 MODE1 register setting.
Specified setting for MODE1 register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_MODE1_FORCED_SLEEP
| #define UARTI2CSPI2_MODE1_FORCED_SLEEP 0x20 |
◆ UARTI2CSPI2_MODE1_RTS_HIZ
| #define UARTI2CSPI2_MODE1_RTS_HIZ 0x08 |
◆ UARTI2CSPI2_MODE1_RX_DISABLE
| #define UARTI2CSPI2_MODE1_RX_DISABLE 0x01 |
◆ UARTI2CSPI2_MODE1_TRNSCV_CTRL
| #define UARTI2CSPI2_MODE1_TRNSCV_CTRL 0x10 |
◆ UARTI2CSPI2_MODE1_TX_DISABLE
| #define UARTI2CSPI2_MODE1_TX_DISABLE 0x02 |
◆ UARTI2CSPI2_MODE1_TX_HIZ
| #define UARTI2CSPI2_MODE1_TX_HIZ 0x04 |
◆ UARTI2CSPI2_MODE2_ECHO_SUPRS
| #define UARTI2CSPI2_MODE2_ECHO_SUPRS 0x80 |
UART I2C SPI 2 MODE2 register setting.
Specified setting for MODE2 register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_MODE2_FIFO_RST
| #define UARTI2CSPI2_MODE2_FIFO_RST 0x02 |
◆ UARTI2CSPI2_MODE2_LOOPBACK
| #define UARTI2CSPI2_MODE2_LOOPBACK 0x20 |
◆ UARTI2CSPI2_MODE2_MULTI_DROP
| #define UARTI2CSPI2_MODE2_MULTI_DROP 0x40 |
◆ UARTI2CSPI2_MODE2_R_FIFO_EMPTY_INV
| #define UARTI2CSPI2_MODE2_R_FIFO_EMPTY_INV 0x08 |
◆ UARTI2CSPI2_MODE2_RST
| #define UARTI2CSPI2_MODE2_RST 0x01 |
◆ UARTI2CSPI2_MODE2_RX_TRIG_INV
| #define UARTI2CSPI2_MODE2_RX_TRIG_INV 0x04 |
◆ UARTI2CSPI2_MODE2_SPECIAL_CHR
| #define UARTI2CSPI2_MODE2_SPECIAL_CHR 0x10 |
◆ UARTI2CSPI2_REVID_MAJOR
| #define UARTI2CSPI2_REVID_MAJOR 0xC0 |
UART I2C SPI 2 REVID register setting.
Specified setting for REVID register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_REVID_MAJOR_MASK
| #define UARTI2CSPI2_REVID_MAJOR_MASK 0xF0 |
◆ UARTI2CSPI2_REVID_MINOR_MASK
| #define UARTI2CSPI2_REVID_MINOR_MASK 0x0F |
◆ UARTI2CSPI2_SET_DATA_SAMPLE_EDGE
| #define UARTI2CSPI2_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE |
Data sample selection.
This macro sets data samples for SPI modules.
- Note
- Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with uarti2cspi2_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.
◆ UARTI2CSPI2_SET_DATA_SAMPLE_MIDDLE
| #define UARTI2CSPI2_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE |
◆ UARTI2CSPI2_SPCHR_IRQ_BREAK
| #define UARTI2CSPI2_SPCHR_IRQ_BREAK 0x10 |
◆ UARTI2CSPI2_SPCHR_IRQ_MULTI_DROP
| #define UARTI2CSPI2_SPCHR_IRQ_MULTI_DROP 0x20 |
UART I2C SPI 2 SPCHR_IRQEN/SPCHR_IRQSTS register setting.
Specified setting for SPCHR_IRQEN/SPCHR_IRQSTS register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_SPCHR_IRQ_XOFF1
| #define UARTI2CSPI2_SPCHR_IRQ_XOFF1 0x04 |
◆ UARTI2CSPI2_SPCHR_IRQ_XOFF2
| #define UARTI2CSPI2_SPCHR_IRQ_XOFF2 0x08 |
◆ UARTI2CSPI2_SPCHR_IRQ_XON1
| #define UARTI2CSPI2_SPCHR_IRQ_XON1 0x01 |
◆ UARTI2CSPI2_SPCHR_IRQ_XON2
| #define UARTI2CSPI2_SPCHR_IRQ_XON2 0x02 |
◆ UARTI2CSPI2_SPI_REG_MASK
| #define UARTI2CSPI2_SPI_REG_MASK 0x1F |
◆ UARTI2CSPI2_SPI_UART_SEL_0
| #define UARTI2CSPI2_SPI_UART_SEL_0 0x00 |
◆ UARTI2CSPI2_SPI_UART_SEL_1
| #define UARTI2CSPI2_SPI_UART_SEL_1 0x20 |
◆ UARTI2CSPI2_SPI_UART_SEL_MASK
| #define UARTI2CSPI2_SPI_UART_SEL_MASK 0x20 |
◆ UARTI2CSPI2_SPI_WRITE_BIT
| #define UARTI2CSPI2_SPI_WRITE_BIT 0x80 |
◆ UARTI2CSPI2_STS_IRQ_CLK_READY
| #define UARTI2CSPI2_STS_IRQ_CLK_READY 0x20 |
◆ UARTI2CSPI2_STS_IRQ_GPI0
| #define UARTI2CSPI2_STS_IRQ_GPI0 0x01 |
◆ UARTI2CSPI2_STS_IRQ_GPI1
| #define UARTI2CSPI2_STS_IRQ_GPI1 0x02 |
◆ UARTI2CSPI2_STS_IRQ_GPI2
| #define UARTI2CSPI2_STS_IRQ_GPI2 0x04 |
◆ UARTI2CSPI2_STS_IRQ_GPI3
| #define UARTI2CSPI2_STS_IRQ_GPI3 0x08 |
◆ UARTI2CSPI2_STS_IRQ_SLEEP
| #define UARTI2CSPI2_STS_IRQ_SLEEP 0x40 |
◆ UARTI2CSPI2_STS_IRQ_TX_EMPTY
| #define UARTI2CSPI2_STS_IRQ_TX_EMPTY 0x80 |
UART I2C SPI 2 STS_IRQEN/STS_IRQSTS register setting.
Specified setting for STS_IRQEN/STS_IRQSTS register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_TXSYNCH_CLK_TO_GPIO
| #define UARTI2CSPI2_TXSYNCH_CLK_TO_GPIO 0x80 |
UART I2C SPI 2 TXSYNCH register setting.
Specified setting for TXSYNCH register of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_TXSYNCH_SYNCH_EN
| #define UARTI2CSPI2_TXSYNCH_SYNCH_EN 0x10 |
◆ UARTI2CSPI2_TXSYNCH_TRIG_DELAY
| #define UARTI2CSPI2_TXSYNCH_TRIG_DELAY 0x20 |
◆ UARTI2CSPI2_TXSYNCH_TRIG_SEL0
| #define UARTI2CSPI2_TXSYNCH_TRIG_SEL0 0x01 |
◆ UARTI2CSPI2_TXSYNCH_TRIG_SEL1
| #define UARTI2CSPI2_TXSYNCH_TRIG_SEL1 0x02 |
◆ UARTI2CSPI2_TXSYNCH_TRIG_SEL2
| #define UARTI2CSPI2_TXSYNCH_TRIG_SEL2 0x04 |
◆ UARTI2CSPI2_TXSYNCH_TRIG_SEL3
| #define UARTI2CSPI2_TXSYNCH_TRIG_SEL3 0x08 |
◆ UARTI2CSPI2_TXSYNCH_TX_AUTO_DIS
| #define UARTI2CSPI2_TXSYNCH_TX_AUTO_DIS 0x40 |
◆ UARTI2CSPI2_UART_SEL_0
| #define UARTI2CSPI2_UART_SEL_0 0 |
UART I2C SPI 2 interface setting.
Specified setting for interface of UART I2C SPI 2 Click driver.
◆ UARTI2CSPI2_UART_SEL_1
| #define UARTI2CSPI2_UART_SEL_1 1 |
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